Lecture 3 | 5 August 2026

Gate Logic

From gate diagrams to Hardware Description Language (HDL).

gate diagrams→composite gates→circuit descriptions→specifications

Where are we in the course?

Give Boolean Functions a Physical Form

Last lectureBoolean functionstruth tables and expressions

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TodayLogic gatesdiagrams, descriptions, and specifications

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Next lectureBoolean arithmeticnumbers and addition

A logic gate gives a physical form to a Boolean function.

Introducing logic gates

A Gate Implements a Boolean Function

Inputsa, b

→AND→

Outputout

A gate is a physical device that implements a Boolean function.

Input pins receive binary values. The gate computes the function and places the result on its output pin.

For every input combination, the output must agree with the function's truth table.

Next: Learn the standard symbols used to draw gates.

Standard gate diagrams

Six Familiar Functions, Six Gate Symbols

AND

OR

NOT

XOR

NAND

NOR

A small circle on the output means negation. The extra curved line distinguishes XOR from OR.

Primitive and composite gates

Primitive Gates Can Build Composite Gates

Primitive gate: a gate available as a basic building block. For our computer, NAND is the primitive gate.

Composite gate: a gate constructed by connecting gates already available to us.

Three-way AND: Implementation A

out = (a · b) · c

Three-way AND: Implementation B

out = a · (b · c)

Exercise 1 | Gate diagrams

Draw the Gate Diagrams

Use only AND, OR, and NOT gates. Label every internal wire.

AXOR(a,b)

a · b + a · b

BNAND(a,b)

a · b

Next: Replace the drawing with a precise textual construction.

Gate-diagram practice

Connect Expressions and Gate Diagrams

1

Write the truth table for a + b · c.

2

Draw its gate diagram using AND, OR, and NOT gates. Label every internal wire.

3

Draw a gate diagram for the same function using only NAND gates.

Next: Describe a circuit precisely without relying on a drawing.

Introducing a circuit-description language

Hardware Description Language

A Hardware Description Language (HDL) describes the parts of a circuit and how their pins are connected.

Draw

Diagrams communicate structure, but large designs become difficult to reproduce and change.

→

Describe

HDL states which parts exist and exactly how their pins are connected.

→

Simulate

Test the described circuit before building a physical device.

We move from diagrams to HDL because a textual description is precise, easier to change, and can be tested by a hardware simulator.

XOR hardware description

Describe the XOR Construction in HDL

CHIP Xor {
  IN a, b;
  OUT out;

  PARTS:
  Not(in=a, out=nota);
  Not(in=b, out=notb);
  And(a=a, b=notb, out=w1);
  And(a=nota, b=b, out=w2);
  Or(a=w1, b=w2, out=out);
}

InterfaceCHIP, IN, OUT

The chip's name and the pins visible to someone using it.

ImplementationPARTS:

The lower-level gates used to build XOR.

ConnectionsNamed pins and wires

Values flow through nota, notb, w1, and w2.

Reading the XOR description

The Header Specifies the Interface

CHIP Xor {
  IN a, b;
  OUT out;

  PARTS:
  Not(in=a, out=nota);
  Not(in=b, out=notb);
  And(a=a, b=notb, out=w1);
  And(a=nota, b=b, out=w2);
  Or(a=w1, b=w2, out=out);
}

Chip nameXor

Input pinsa, b

Output pinout

The interface tells us how to connect and use the chip.

Reading the XOR description

The PARTS Section Connects Lower-Level Gates

CHIP Xor {
  IN a, b;
  OUT out;

  PARTS:
  Not(in=a, out=nota);
  Not(in=b, out=notb);
  And(a=a, b=notb, out=w1);
  And(a=nota, b=b, out=w2);
  Or(a=w1, b=w2, out=out);
}

a→Not→nota

b→Not→notb

a, notb→And→w1

nota, b→And→w2

w1, w2→Or→out

nota, notb, w1, and w2 are internal wires, created by naming connections.

Testing the XOR description

Test Every XOR Input Combination

Test script

load Xor.hdl,
output-list a, b, out;

set a 0, set b 0, eval, output;
set a 0, set b 1, eval, output;
set a 1, set b 0, eval, output;
set a 1, set b 1, eval, output;

→

Produced output

a	b	out
0	0	0
0	1	1
1	0	1
1	1	0

→

VerifyDoes the produced output match XOR?

All four possible inputs are tested.

Next: State clearly what every chip is required to do.

Defining required behaviour

What Is a Specification?

A specification states the chip's name, inputs, outputs, and required function. It says what the chip must do, independently of how it is built.

Example specification

Chip name: NotInputs: inOutputs: outFunction: If in=0, then out=1; else out=0.

Chip name: NandInputs: a, bOutputs: outFunction: If a=1 and b=1, then out=0; else out=1.

Chip name: AndInputs: a, bOutputs: outFunction: If a=1 and b=1, then out=1; else out=0.

Chip name: OrInputs: a, bOutputs: outFunction: If a=1 or b=1, then out=1; else out=0.

Chip name: XorInputs: a, bOutputs: outFunction: If a and b differ, then out=1; else out=0.

A gate for choosing an input

Multiplexor: Choose One Input

A multiplexor (Mux) uses the selection bit sel to choose which input reaches out.

Symbolic representation

Truth table

a	b	sel	out
0	0	0	0
0	1	0	0
1	0	0	1
1	1	0	1
0	0	1	0
0	1	1	1
1	0	1	0
1	1	1	1

Abbreviated truth table

sel	out
0	a
1	b

Specification

Chip name: MuxInputs: a, b, selOutputs: outFunction: If sel=0, then out=a; else out=b.

Let a=1 and b=0. Predict out for both values of sel.

sel=0: out=1 | sel=1: out=0

Exercise 2 | Multiplexor construction

Build a Mux in Two Ways

AUsing AND, OR, and NOT

Draw a gate diagram for Mux and then write its HDL description.

BUsing NAND only

Draw a NAND-only gate diagram for Mux and then write its HDL description.

Chip name: MuxInputs: a, b, selOutputs: outFunction: If sel=0, then out=a; else out=b.

Use the specification to check both implementations for all eight input combinations.

A gate for choosing a destination

Demultiplexor: Choose One Destination

A demultiplexor (DMux) sends in to output a or output b. The unselected output is 0.

Symbolic representation

Truth table

in	sel	a	b
0	0	0	0
1	0	1	0
0	1	0	0
1	1	0	1

Abbreviated truth table

sel	a	b
0	in	0
1	0	in

Specification

Chip name: DMuxInputs: in, selOutputs: a, bFunction: If sel=0, then a=in and b=0; else a=0 and b=in.

Next: Apply one gate operation to a group of bits.

Introducing multi-bit gates

A Multi-Bit Gate Operates on a Bus

A bus is a group of parallel wires. A 16-bit bus carries sixteen binary values at the same time.

Example: multi-bit NOT

Chip name: Not16Inputs: in[16]Outputs: out[16]Function: For every position i, out[i]=Not(in[i]).

Example input:0000000000000011Required output:1111111111111100

Other examples

Chip name: And16Inputs: a[16], b[16]Outputs: out[16]Function: For every i, out[i]=And(a[i],b[i]).

Chip name: Or16Inputs: a[16], b[16]Outputs: out[16]Function: For every i, out[i]=Or(a[i],b[i]).

Chip name: Mux16Inputs: a[16], b[16], selOutputs: out[16]Function: If sel=0, then out=a; else out=b.

Each bit position is processed independently; neighboring positions do not interact.

Introducing a multi-way gate

Or8Way Reduces Eight Inputs to One Bit

in[0]in[1]...in[7]

→

Or8WayOR all inputs

→

out

Chip name: Or8WayInputs: in[8]Outputs: outFunction: If at least one input bit is 1, then out=1; else out=0.

Or16 operates pairwise on two buses. Or8Way combines eight input bits into one output bit.

Multi-way, multi-bit selection

Mux4Way16 and Mux8Way16

Chip name: Mux4Way16Inputs: a[16], b[16], c[16], d[16], sel[2]Outputs: out[16]Function: The two-bit selector chooses one of four input buses.

sel	out
00	a
01	b
10	c
11	d

Chip name: Mux8Way16Inputs: a[16] through h[16], sel[3]Outputs: out[16]Function: The three-bit selector chooses one of eight input buses.

Why these selector widths?

Two bits encode four choices: 00 to 11.

Three bits encode eight choices: 000 to 111.

Multi-way routing

DMux4Way and DMux8Way

Chip name: DMux4WayInputs: in, sel[2]Outputs: a, b, c, dFunction: Route in to the selected output; set the other outputs to 0.

sel	a	b	c	d
00	in	0	0	0
01	0	in	0	0
10	0	0	in	0
11	0	0	0	in

Chip name: DMux8WayInputs: in, sel[3]Outputs: a, b, c, d, e, f, g, hFunction: Route in to the selected output; set the other seven outputs to 0.

Three selector bits choose one of eight destinations.

Next: Implement the specified gates in HDL.

Exercise 3 | Complete at home

Implement the Following Gates in HDL

For every named chip below, write an HDL implementation using only NAND or chips that you have already implemented from NAND.

Two-input and selector gatesNot, And, Or, Xor, Mux, DMux

Gates operating on busesNot16, And16, Or16, Mux16

Gates with several inputs or outputsOr8Way, Mux4Way16, Mux8Way16, DMux4Way, DMux8Way

For each chip:

Read its specification.
Plan the internal gate connections.
Write the HDL.
Run the supplied test script and correct every failing case.

Review questions

Check Your Understanding

1

For a Mux with a=0 and b=1, find out for both values of sel.

2

For a DMux with in=1, find (a,b) for both values of sel.

3

If in[16]=0000000000000101, what is the output of Not16?

4

Why does Mux8Way16 need three selector bits?

5

How is Or8Way different from Or16?

6

For DMux4Way with in=1 and sel=10, write a,b,c,d.

Next lecture | Boolean Arithmetic

Represent Numbers and Perform Arithmetic

How can gates represent numbers and perform operations such as addition and multiplication?

binary numbers→addition→carry→multiplication

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